Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/83937
Title: Evaluating the efficiency of DSP Block synthesis inference from flow graphs
Authors: Ronak, Bajaj..
Fahmy, Suhaib A.
Issue Date: 2012
Abstract: The embedded DSP Blocks in FPGAs have become significantly more capable in recent generations of devices. While vendor synthesis tools can infer the use of these resources, the efficiency of this inference is not guaranteed. Specific language structures are suggested for implementing standard applications but others that do not fit these standard designs can suffer from inefficient synthesis inference. In this paper, we demonstrate this effect by synthesising a number of arithmetic circuits, showing that standard code results in a significant resource and timing overhead compared to considered use of DSP Blocks and their plethora of configuration options through custom instantiation.
URI: https://hdl.handle.net/10356/83937
http://hdl.handle.net/10220/12874
DOI: 10.1109/FPL.2012.6339163
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:SCSE Conference Papers

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