Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/84004
Full metadata record
DC FieldValueLanguage
dc.contributor.authorLiu, Nanen
dc.contributor.authorChong, Kwen-Siongen
dc.contributor.authorHo, Weng-Gengen
dc.contributor.authorGwee, Bah Hweeen
dc.contributor.authorChang, Joseph Sylvesteren
dc.date.accessioned2017-02-23T07:11:12Zen
dc.date.accessioned2019-12-06T15:36:17Z-
dc.date.available2017-02-23T07:11:12Zen
dc.date.available2019-12-06T15:36:17Z-
dc.date.issued2016en
dc.identifier.citationLiu, N., Chong, K.-S., Ho, W.-G., Gwee, B. H., & Chang, J. S. (2016). Low Normalized Energy Derivation Asynchronous Circuit Synthesis Flow through Fork-Join Slack Matching for Cryptographic Applications. 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 850-853.en
dc.identifier.urihttps://hdl.handle.net/10356/84004-
dc.description.abstractIn this paper, an automatic synthesis flow of asynchronous (async) Quasi-Delay-Insensitive (QDI) circuits for cryptographic applications is presented. The synthesis flow accepts Verilog netlists as primary inputs, in part leverages on commercial electronic design automation tools for synthesis and verifications, and relies heavily on the proposed translation processes for async netlist conversion and optimization. Particularly, a three-step synchronous-to-asynchronous-direct-translation (SADT) process is proposed. The first step is to translate a Verilog netlist into a direct circuit graph, allowing us to model QDI pipelines for performance analysis based on the same netlist function. Second, graph coarsening in combination with dynamic programing is adopted to analyze the fork-join slack matching of the QDI pipelines, aiming to balance the pipeline depths in any fork-join pipelines to optimize the system performance, and to reduce energy variations of the overall pipelines to against power-analysis-attack. The last step is to insert async local controllers/gates to ensure the async circuits consistent with QDI protocol, hence enhancing its timing robustness to accommodate Process-Voltage-Temperature variations. We show that, on the basis of simulations on the ISCAS benchmark circuits, the QDI circuits based on our proposed automatic synthesis flow are on average 20% faster and feature 30% less normalized energy derivations than un-optimized circuits.en
dc.description.sponsorshipASTAR (Agency for Sci., Tech. and Research, S’pore)en
dc.format.extent4 p.en
dc.language.isoenen
dc.rights© 2016 European Design and Automation Association (EDAA). This paper was published in 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) and is made available as an electronic reprint (preprint) with permission of EDAA. The published version is available at: [http://ieeexplore.ieee.org/document/7459427/]. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper is prohibited and is subject to penalties under law.en
dc.subjectIntegrated circuit modelingen
dc.subjectCryptographyen
dc.titleLow Normalized Energy Derivation Asynchronous Circuit Synthesis Flow through Fork-Join Slack Matching for Cryptographic Applicationsen
dc.typeConference Paperen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.contributor.conference2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)en
dc.contributor.researchTemasek Laboratoriesen
dc.description.versionPublished versionen
dc.identifier.urlhttp://ieeexplore.ieee.org/document/7459427/en
item.grantfulltextopen-
item.fulltextWith Fulltext-
Appears in Collections:EEE Conference Papers
TL Journal Articles

Page view(s) 50

403
Updated on May 20, 2022

Download(s) 50

65
Updated on May 20, 2022

Google ScholarTM

Check

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.