Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/84007
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dc.contributor.authorHo, Weng-Gengen
dc.contributor.authorLiu, Nanen
dc.contributor.authorNe, Kyaw Zwa Lwinen
dc.contributor.authorChong, Kwen-Siongen
dc.contributor.authorGwee, Bah Hweeen
dc.contributor.authorChang, Joseph Sylvesteren
dc.date.accessioned2016-12-05T04:42:51Zen
dc.date.accessioned2019-12-06T15:36:20Z-
dc.date.available2016-12-05T04:42:51Zen
dc.date.available2019-12-06T15:36:20Z-
dc.date.issued2016en
dc.identifier.citationHo, W.-G., Liu, N., Ne, K. Z. L., Chong, K.-S., Gwee, B. H., & Chang, J. S. (2016). High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits. IEEE International Symposium on Circuits and Systems, 1762-1765.en
dc.identifier.urihttps://hdl.handle.net/10356/84007-
dc.description.abstractWe propose a novel Template-based Cell-Interleave Pipeline (TCIP) approach for generating high performance and yet low overhead asynchronous-logic (async) quasi-delay-insensitive (QDI) circuits. Our TCIP approach exploits the characteristics of the four prevalent QDI cell templates, namely Weak-Conditioned Half-Buffer (WCHB), Pre-Charged HalfBuffer (PCHB), Autonomous Signal-Validity Half-Buffer (ASVHB), and Sense-Amplifier Half-Buffer (SAHB), and then strategically interleave these template cells to form a composite pipeline. There are three main features in our TCIP approach. First, all QDI cell templates are first standardized with the same interface signals, and their corresponding cells are characterized in terms of transistor count, cycle time and energy dissipation for ease of comparison/selection/replacement. Second, our TCIP approach prioritizes the speed requirement when forming the initial pipeline circuits, and then subsequently reduces circuit overheads by interleaving various template cells without compromising the speed significantly. Third, the final optimized QDI pipeline circuit inherently features high robustness against process-voltage-temperature (PVT) variations, hence suitable for dynamic-voltage-scaling (DVS) operation. By means of 65nm CMOS process, we demonstrate a 4-bit pipeline tree adder based on the proposed TCIP approach, and benchmark it against the WCHB, PCHB, ASVHB and SAHB counterparts. These five designs feature same high operational robustness, nonetheless the design based on our TCIP approach is more competitive. Particularly, the designs based on reported approaches are, on average, ~1.22× more transistor count, ~1.21× slower and ~1.22× higher energy dissipation. Furthermore, under DVS operation from 1.2V to 0.3V, our proposed TCIP adder can reduce up to 88% energy for non-speed critical applications.en
dc.description.sponsorshipASTAR (Agency for Sci., Tech. and Research, S’pore)en
dc.format.extent4 p.en
dc.language.isoenen
dc.rights© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/ISCAS.2016.7538909].en
dc.subjectVoltage stabilizing circuitsen
dc.subjectAsynchronous logicen
dc.titleHigh Performance Low Overhead Template-based Cell-Interleave Pipeline (TCIP) for Asynchronous-Logic QDI Circuitsen
dc.typeConference Paperen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.contributor.conferenceIEEE International Symposium on Circuits and Systems (ISCAS)en
dc.contributor.researchCentre for Integrated Circuits and Systemsen
dc.identifier.doi10.1109/ISCAS.2016.7538909en
dc.description.versionAccepted versionen
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Appears in Collections:EEE Conference Papers
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