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Title: Counteracting differential power analysis: Hiding encrypted data from circuit cells
Authors: Chong, Kwen-Siong
Ne, Kyaw Zwa Lwin
Ho, Weng-Geng
Liu, Nan
Akbar, Ali H.
Gwee, Bah-Hwee
Chang, Joseph Sylvester
Keywords: solid state circuits
integrated circuits
Issue Date: 2015
Source: Chong, K.-S., Ne, K. Z. L., Ho, W.-G., Liu, N., Akbar, A. H., Gwee, B.-H., et al. (2015). Counteracting differential power analysis: Hiding encrypted data from circuit cells. 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 15506250-.
Abstract: We propose a balanced Pre-Charge Static Logic (PCSL) circuit style for asynchronous systems, and compare it against other reported circuit styles to counteract differential power analysis (DPA). Our study shows that all these circuit styles (including our balanced PCSL) dissipate different energy due to data-dependency, and hence balancing the energy of circuits embodying these circuit styles remains challenging. However, in view of low circuit overheads and asynchronous operations (with noise generation), our balanced PCSL is still competitive in terms of DPA-resistance, requiring 3.5x less power traces than its NULL convention logic counterpart.
DOI: 10.1109/EDSSC.2015.7285109
Rights: © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Conference Papers

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