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Title: Flip-Flop SR Latch Logic Operation for Spin Orbit Torque-Magnetic Tunnel Junction Circuitry
Authors: Loy, Desmond Jia Jun
Issue Date: 2016
Source: Loy, D. J. J. (2016, March). Flip-Flop SR Latch Logic Operation for Spin Orbit Torque-Magnetic Tunnel Junction Circuitry. Presented at Discover URECA @ NTU poster exhibition and competition, Nanyang Technological University, Singapore.
Abstract: In recent years, spin transfer torque (STT)-magnetic random access memory (MRAM) was seen as one of the most promising candidates for next-generation non-volatile memory. STT-MRAM was seen as a potential candidate to replace complementary metal oxide semiconductor (CMOS)-based memory in the field of logic-in-memory. However, STT-MRAM also faces challenges such as high energy consumption and weakened reliability due to a common access path for both read and write operations. This compels the search for a new spintronic concept known as spin orbit torque (SOT)-MRAM. The core of a MRAM is the magnetic tunnel junction (MTJ) cell. A SOT-MTJ is a three-terminal device which has its read and write paths isolated, and it consist of better overall properties as compared to an STT-MTJ, making SOT-MTJ a suitable novel paradigm for logic applications. In this work, we demonstrate a prototype SOT-based MTJ SR-latch circuit which has faster switching time and shorter energy delay as compared to conventional semiconductor counterparts. [2nd Award]
Rights: © 2016 The Author(s).
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:URECA Posters

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