Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/84207
Full metadata record
DC FieldValueLanguage
dc.contributor.authorPammu, Ali Akbaren
dc.contributor.authorChong, Kwen-Siongen
dc.contributor.authorNe, Kyaw Zwa Lwinen
dc.contributor.authorGwee, Bah Hweeen
dc.date.accessioned2016-11-30T09:27:36Zen
dc.date.accessioned2019-12-06T15:40:33Z-
dc.date.available2016-11-30T09:27:36Zen
dc.date.available2019-12-06T15:40:33Z-
dc.date.issued2016en
dc.identifier.citationPammu, A. A., Chong, K. S., Ne, K. Z. L., & Gwee, B. H. (2016). High Secured Low Power Multiplexer-LUT Based AES S-Box Implementation. 2016 International Conference on Information Systems Engineering (ICISE).en
dc.identifier.urihttps://hdl.handle.net/10356/84207-
dc.description.abstractWe propose a Multiplexer Look-Up-Table (MLUT) based Substitution-Box (S-Box) implementation for the Advanced Encryption Standard (AES) algorithm. There are two key features in the proposed MLUT based S-Box. First, it is implemented based on 256-byte to 1-byte multiplexer with a 256-byte memory instead of the conventional implementation of employing multiplication inversion in GF(28) and affine transformation. Thus, our proposed S-Box is simpler in circuit implementation and lower in power dissipation. Second, our S-Box is 30× more secured against the Side Channel Attack (SCA) based on Correlation Power Analysis (CPA), as our proposed S-Box exhibits smaller variance in its power dissipation profile for different processed data. Based on the measurement results of AES-128 implemented on the Sakura-X FPGA board, our proposed S-Box dissipates only 1.9mW and features 5.5× lower power than the conventional S-Box implementation. Our proposed MLUT S-Box design is also highly secured as the CPA attack on the AES with our proposed S-Box implementation requires 13540 power traces. This is significantly higher than the conventional S-Box which requires only 445 power traces to uncover the same secrete key.en
dc.description.sponsorshipASTAR (Agency for Sci., Tech. and Research, S’pore)en
dc.format.extent5 p.en
dc.language.isoenen
dc.rights© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/ICISE.2016.11].en
dc.subjectPower dissipationen
dc.subjectLogic gatesen
dc.titleHigh Secured Low Power Multiplexer-LUT Based AES S-Box Implementationen
dc.typeConference Paperen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.contributor.conference2016 International Conference on Information Systems Engineering (ICISE)en
dc.contributor.researchCentre for Integrated Circuits and Systemsen
dc.identifier.doi10.1109/ICISE.2016.11en
dc.description.versionAccepted versionen
item.fulltextWith Fulltext-
item.grantfulltextopen-
Appears in Collections:EEE Conference Papers
Files in This Item:
File Description SizeFormat 
High Secured Low Power.pdfMain Article598.83 kBAdobe PDFThumbnail
View/Open

SCOPUSTM   
Citations

12
checked on Sep 4, 2020

WEB OF SCIENCETM
Citations

9
checked on Sep 18, 2020

Page view(s)

238
checked on Sep 24, 2020

Download(s)

118
checked on Sep 24, 2020

Google ScholarTM

Check

Altmetric


Plumx

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.