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Title: A high speed open source controller for FPGA Partial Reconfiguration
Authors: Vipin, Kizheppatt.
Fahmy, Suhaib A.
Keywords: DRNTU::Engineering::Computer science and engineering
Issue Date: 2012
Source: Vipin, K., & Fahmy, S. A. (2012). A high speed open source controller for FPGA Partial Reconfiguration. 2012 International Conference on Field-Programmable Technology (FPT), pp.61-66.
Abstract: Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. PR is an important enabler for implementing adaptive systems. However, the design of such systems can be challenging, and this is especially true of the configuration controller. The generally supported methods and IP have low throughput, resulting in long configuration time that precludes PR from systems where this operation needs to be fast. In this paper, we present a high-speed configuration controller that provides several features useful in adaptive systems. The design has been released for use by the wider research community.
DOI: 10.1109/FPT.2012.6412113
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:SCSE Conference Papers

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