Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/84605
Title: 3-state BTL closed-loop PWM Class D amplifiers
Authors: He, Huiqiao
Ge, Tong
Guo, Linfei
Chang, Joseph Sylvester
Keywords: Class D amplifiers
Bridge-tied-load
Issue Date: 2016
Source: He, H., Ge, T., Guo, L., & Chang, J. S. (2016). 3-state BTL closed-loop PWM Class D amplifiers. Analog Integrated Circuits and Signal Processing, 88(2), 255-266.
Series/Report no.: Analog Integrated Circuits and Signal Processing
Abstract: One of the shortcomings of a number of Class D amplifiers (CDAs) designs is their susceptibility to supply noise, quantified by Power Supply Rejection Ratio (PSRR). Reported investigations thereto to-date remain incomplete/over-simplified, particularly the assumption that the AC ground is noise-less and a simplified fully-differential integrator model. In this paper, the effect of supply noise in the AC ground to PSRR is analytically investigated, and the associated analytical expressions derived. Of specific interest, the analysis is applied to the ubiquitous 3-state Bridge-tied-load (BTL) closed-loop PWM CDA, taking into consideration not only the effect of the non-ideal AC ground, but also the effect of the resistor and capacitor mismatch based on a realistic fully-differential integrator model. Further, the PSRR analysis of 3-state BTL closed-loop CDAs has to date been limited to the single-feedback topology and in this paper, extended to the double-feedback topology. These analyses and derived equations herein are useful as they provide valuable insights to CDA designers into the PSRR mechanisms—for example, the counter-intuitive observation that the CDA with 1st-order integrators provides similar or better PSRR than the CDA with 2nd-order integrators if both CDAs are designed to the same carrier attenuation—including the effect of various circuit parameters, and ensuing trade-offs. The derived analytical expressions are verified by means of HSPICE simulations and on the basis of practical measurements on discretely-realized CDAs.
URI: https://hdl.handle.net/10356/84605
http://hdl.handle.net/10220/41904
ISSN: 0925-1030
DOI: 10.1007/s10470-016-0750-0
Rights: © 2016 Springer Science+Business Media New York. This is the author created version of a work that has been peer reviewed and accepted for publication by Analog Integrated Circuits and Signal Processing, Springer. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [http://dx.doi.org/10.1007/s10470-016-0750-0].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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