Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/84655
Title: A 1.2V 80MS/S sample and hold for ADC applications
Authors: Reddy, Y. Sunil Gavaskar.
Liter, Siek.
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2012
Source: Reddy, Y. S. G., & Liter, S. (2012). A 1.2V 80MS/S sample and hold for ADC applications. 2012 International Conference on Devices, Circuits and Systems (ICDCS).
Abstract: This Paper presents the design of low voltage sample and hold amplifier for analog to digital converter applications. The proposed design uses double sampling technique to increase the sampling rate, reliable bootstrap switch to reduce switch on resistance and to extend linear range of switch. A rail-to-rail ICMR op-amp, is used to extend the input operating range. The designed sample and hold operates at 80MS/s from 1.2V supply. The circuits are designed using CSM 0.18um technology in cadence environment and power consumption estimated was 4.15mW.
URI: https://hdl.handle.net/10356/84655
http://hdl.handle.net/10220/12138
DOI: 10.1109/ICDCSyst.2012.6188668
Rights: © 2012 IEEE.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Conference Papers

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