Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/84782
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dc.contributor.authorKim, Tony Tae-Hyoungen
dc.contributor.authorLiu, Jason.en
dc.contributor.authorKeane, John.en
dc.contributor.authorKim, Chris H.en
dc.date.accessioned2010-08-20T04:01:40Zen
dc.date.accessioned2019-12-06T15:51:05Z-
dc.date.available2010-08-20T04:01:40Zen
dc.date.available2019-12-06T15:51:05Z-
dc.date.copyright2008en
dc.date.issued2008en
dc.identifier.citationKim. T. H., Liu, J., Keane, J., & Kim, C. H. (2008). A 0.2 V, 480 kb subthreshold SRAM with 1 k cells per bitline for ultra-low-voltage computing. IEEE Journal of Solid State Circuits. 43(2), 518-529.en
dc.identifier.issn0018-9200en
dc.identifier.urihttps://hdl.handle.net/10356/84782-
dc.identifier.urihttp://hdl.handle.net/10220/6332en
dc.description.abstractA 2 W, 100 kHz, 480 kb subthreshold SRAM operating at 0.2 V is demonstrated in a 130 nm CMOS process. A 10-T SRAM cell allows 1 k cells per bitline by eliminating the data-dependent bitline leakage. A virtual ground replica scheme is proposed for logic “0” level tracking and optimal sensing margin in read buffers. Utilizing the strong reverse short channel effect in the subthreshold region improves cell writability and row decoder performance due to the increased current drivability at a longer channel length. The sizing method leads to an equivalent write wordline voltage boost of 70 mV and a delay improvement of 28% in the row decoder compared to the conventional sizing scheme at 0.2 V. A bitline writeback scheme was used to eliminate the pseudo-write problem in unselected columns.en
dc.format.extent12 p.en
dc.language.isoenen
dc.relation.ispartofseriesIEEE journal of solid state circuitsen
dc.rights© 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.en
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systemsen
dc.titleA 0.2 V, 480 kb subthreshold SRAM with 1 k cells per bitline for ultra-low-voltage computingen
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.identifier.doi10.1109/JSSC.2007.914328en
dc.description.versionPublished versionen
item.grantfulltextopen-
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