Low voltage adiabatic circuits with 2N2P charge recovery logic

Abstract

Low power dissipation has become an very important objective in VLSI design. This project is to analyze the 2N2P charge recovery circuit logic which has remarkable reduction in circuit power dissipation. The charge recovery logic consist of PMOS loads and NMOS pull-down transistors. The NMOS transistors get differential positive and negative inputs; the cross-coupled PMOS transistors is connected to the power-clock supply. [2nd Award]