Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/84921
Title: Stack sizing for optimal current drivability in subthreshold circuits
Authors: Kim, Tony Tae-Hyoung
Keane, John.
Eom, Hanyong.
Sapatnekar, Sachin.
Kim, Chris H.
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2008
Source: Keane, J., Eom, H., Kim, T. H., Sapatnekar, S., & Kim, C. H., (2008). Stack Sizing for Optimal Current Drivability in Subthreshold Circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16(5), 598-602.
Series/Report no.: IEEE transactions on very large scale integration (VLSI) systems
Abstract: Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors in the subthreshold region are significantly different from those in strong inversion. This presents new challenges in design optimization, particularly in complex gates with stacks of transistors. In this paper, we present a framework for choosing the optimal transistor stack sizing factors in terms of current drivability for subthreshold designs. We derive a closed-form solution for the correct sizing of transistors in a stack, both in relation to other transistors in the stack, and to a single device with equivalent current derivability. Simulation results show that our framework provides a performance benefit ranging up to more than 10% in certain critical paths.
URI: https://hdl.handle.net/10356/84921
http://hdl.handle.net/10220/6269
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2008.917571
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Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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