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|Title:||Monolithic integration of Si-CMOS and III-V-on-Si through direct wafer bonding process||Authors:||Lee, Kwang Hong
Sasangka, Wardhana Aji
Goh, Shuh Chin
Lee, Kenneth E.
Fitzgerald, Eugene A.
Tan, Chuan Seng
|Issue Date:||2017||Source:||Lee, K. H., Wang, Y., Wang, B., Zhang, L., Sasangka, W. A., Goh, S. C., et al. (2018). Monolithic integration of Si-CMOS and III-V-on-Si through direct wafer bonding process. IEEE Journal of the Electron Devices Society, 6, 571-578.||Series/Report no.:||IEEE Journal of the Electron Devices Society||Abstract:||Integration of silicon-complementary metal oxide-semiconductor (Si-CMOS) and III-V compound semiconductors (with device structures of either InGaAs HEMT, AlGaInP LED, GaN HEMT, or InGaN LED) on a common Si substrate is demonstrated. The Si-CMOS layer is temporarily bonded on a Si handle wafer. Another III-V/Si substrate is then bonded to the Si-CMOS containing handle wafer. Finally, the handle wafer is released to realize the Si-CMOS on III-V/Si substrate. For GaN HEMT or LED on Si substrate, additional wafer bonding step is required to replace the fragile Si (111) substrate after high temperature GaN growth with a new Si (001) wafer to improve the robustness of the GaN/Si wafers. Through this substrate replacement step, the bonded wafer pair can survive the subsequent processing steps. The monolithic integration of Si-CMOS + III-V devices on a common Si platform enables new generation of systems with more functionality, better energy efficiency, and smaller form factor.||URI:||https://hdl.handle.net/10356/86269
|ISSN:||2168-6734||DOI:||10.1109/JEDS.2017.2787202||Rights:||© 2017 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Journal Articles|
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