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dc.contributor.authorGu, Chenjieen
dc.contributor.authorAng, Diing Shenpen
dc.contributor.authorGao, Yuanen
dc.contributor.authorGu, Renyuanen
dc.contributor.authorZhao, Ziqien
dc.contributor.authorZhu, Chaoen
dc.identifier.citationGu, C., Ang, D. S., Gao, Y., Gu, R., Zhao, Z., & Zhu, C. (2017). A vacancy-interstitial defect pair model for positive-bias temperature stress-induced electron trapping transformation in the high-κ gate n-MOSFET. IEEE Transactions on Electron Devices, 64(6), 2505-2511.en
dc.description.abstractRecent device reliability studies have observed the shallow-to-deep transformation of electron-trap states under positive-bias temperature stressing. Being two typical types of defects in the high-κ oxide, the oxygen vacancy and oxygen interstitial have been investigated in many simulations, but results have indicated that the corresponding defect levels are either too shallow or too deep and fail to explain the experimental observation. Here, we propose a vacancy-interstitial (V o -O i ) model. By tuning the relative positions of V o and O i , we show that the charge trap level of the defect pair can be adjusted continuously within the HfO 2 bandgap. This allows us to depict a possible atomic picture for understanding the shallow-to-deep transformation of electron trapping.en
dc.description.sponsorshipMOE (Min. of Education, S’pore)en
dc.format.extent7 p.en
dc.relation.ispartofseriesIEEE Transactions on Electron Devicesen
dc.rights© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [].en
dc.subjectCMOS Reliabilityen
dc.subjectDynamic Bias Temperature Instability (BTI)en
dc.titleA vacancy-interstitial defect pair model for positive-bias temperature stress-induced electron trapping transformation in the high-κ gate n-MOSFETen
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
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