Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/87458
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dc.contributor.authorFu, Qundongen
dc.date.accessioned2018-11-30T05:11:00Zen
dc.date.accessioned2019-12-06T16:42:21Z-
dc.date.available2018-11-30T05:11:00Zen
dc.date.available2019-12-06T16:42:21Z-
dc.date.issued2018en
dc.identifier.citationFu, Q. (2018). Synthesis and device applications of atom-thin semiconducting chalcogenides. Doctoral thesis, Nanyang Technological University, Singapore.en
dc.identifier.urihttps://hdl.handle.net/10356/87458-
dc.description.abstractThe ongoing scaling of silicon-based metal-oxide-semiconductor field-effect transistor is hindered by the serious short channel effect in sub-10 nm channel length. The discovery of graphene raised the booming development of 2D materials which have the merits of high mobility, efficient current regulation and high level of integration. However, the performance of 2D materials in electronic and optoelectronic applications still need to be improved, which is the aim, such as high mobility, high sensitivity and high gain, of this thesis. Firstly, the aim of the first work is to improve the FET performance of MoS2 via contact engineering of metal/semiconductor (M/S) vdW heterostructure with an atomically sharp interface prepared by CVD method. M/S vdW contact has shown great advantages, such as good stability, larger size and clean interface, in the improvement of M/S contact. In the CVD synthesis, M/S TMDC vdW heterostructures were less explored due to the high melting points and low chemical reactivity of metal oxide feedstocks and the crystal lattice mismatch. In this work, for the first time, the M/S TMDC vdW heterostructure NbS2/MoS2 was synthesized via a one-step halide-assisted CVD method. OM, SEM and XPS were used to identify the M/S vdW heterostructure. This method provides high crystal quality and clean interface of the heterostructure, confirmed by STEM characterization. A growth mechanism was proposed that MoS2 finished the growth first and subsequently served as a superior substrate for the growth of NbS2, verified by Raman mapping. The PL and device measurement provided physical supports of the M/S vdW heterostructure. Secondly, the aim of the second work is to achieve high photodetector performance of Bi2O2Se via transferring high-quality Bi2O2Se onto 280 nm SiO2/Si substrate (Si substrate) by a non-corrosive method. In the chasing of high-mobility 2D semiconductors, competitive candidate CVD-grown Bi2O2Se has superior stability and high mobility, which surpass that of MoS2. However, the photodetector performance of Bi2O2Se regarding on/off ratio and specific detectivity was limited by the large dark current. Compared with f-mica substrate, Si substrate possesses inherent back gating, which could be used to reduce the dark current. However, the hazardous and corrosive HF will etch Bi2O2Se during the transfer, which has been verified by OM, Raman and STEM characterizations. Therefore, a non-corrosive PS-assisted method was developed. The as-transferred Bi2O2Se retained a high quality and showed ultrasensitive phototransistors performance, including high responsivity of 3.5×104 AW−1, high photoconductive gain of 8×104, and fast response rate of sub-millisecond. On Si substrate, the dark current could be reduced to several pA via back gating, which yields an ultrahigh specific detectivity of 9.0×1013 Jones. This is one of the highest values among 2D material photodetectors and two orders of magnitude higher than that of other CVD-grown 2D materials. Thirdly, the aim of this work is to improve the performance and stability of the CMOS inverters based on 2D semiconductors. Although many 2D semiconductors have shown high CMOS inverter performance, such as MoS2, WSe2, MoTe2, their stability is not satisfactory. In this work, CMOS inverters based on high-mobility and stable n-type Bi2O2Se were demonstrated with clear signal inversion on both f-mica and silicon substrate. On f-mica substrate, under the gating of ion liquid, a gain of 3.5 can be obtained at the supply voltage of only 1.0 V. Dynamic voltage response at the frequency of 100 Hz shows good response with almost no voltage lose. On silicon substrate, the CMOS inverter showed a high gain of 2.2 at the supply voltage of 5.0 V, a high noise margin of 5.2 VDD and a low power consumption at the order of 10-9 W.en
dc.format.extent187 p.en
dc.language.isoenen
dc.subjectDRNTU::Engineering::Materialsen
dc.titleSynthesis and device applications of atom-thin semiconducting chalcogenidesen
dc.typeThesisen
dc.contributor.supervisorLiu Zhengen
dc.contributor.schoolSchool of Materials Science & Engineeringen
dc.description.degreeDoctor of Philosophyen
dc.identifier.doi10.32657/10220/46749en
item.grantfulltextopen-
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Appears in Collections:MSE Theses
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