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dc.contributor.authorQiu, Leien
dc.contributor.authorTang, Kaien
dc.contributor.authorZheng, Yuanjinen
dc.contributor.authorSiek, Literen
dc.identifier.citationQiu, L., Tang, K., Zheng, Y., & Siek, L. (2017). Meta-stability immunity technique for high speed SAR ADCs. Electronics Letters, 53(5), 300-302.en
dc.description.abstractAn 8-bit 4 GS/s 8-channel time-interleaved successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. To enhance the ENOB (effective number of bits), a meta-stability immunity technique is proposed, which utilises pre-installation to eliminate uncertain decision. The technique has negligible design overhead in terms of power and silicon area. The ADC chip was fabricated in a 65 nm CMOS technology. It achieves an ENOB of 7.45 bits, with 48 mW power consumption and an area of 0.075 mm2.en
dc.format.extent2 p.en
dc.relation.ispartofseriesElectronics Lettersen
dc.rights© 2017 Institution of Engineering and Technology. This paper was published in Electronics Letters and is made available as an electronic reprint (preprint) with permission of Institution of Engineering and Technology.. The published version is available at: []. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper is prohibited and is subject to penalties under law.en
dc.subjectAnalogue-digital Conversionen
dc.subjectCircuit Stabilityen
dc.titleMeta-stability immunity technique for high speed SAR ADCsen
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.description.versionPublished versionen
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