Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/87784
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dc.contributor.authorJha, Saurabhen
dc.contributor.authorHe, Bingshengen
dc.contributor.authorLu, Mianen
dc.contributor.authorCheng, Xuntaoen
dc.contributor.authorHuynh, Huynh Phungen
dc.date.accessioned2018-12-05T08:27:28Zen
dc.date.accessioned2019-12-06T16:49:25Z-
dc.date.available2018-12-05T08:27:28Zen
dc.date.available2019-12-06T16:49:25Z-
dc.date.issued2015en
dc.identifier.citationJha, S., He, B., Lu, M., Cheng, X., & Huynh, H. P. (2015). Improving main memory hash joins on Intel Xeon Phi processors. Proceedings of the VLDB Endowment, 8(6), 642-653. doi:10.14778/2735703.2735704en
dc.identifier.issn2150-8097en
dc.identifier.urihttps://hdl.handle.net/10356/87784-
dc.identifier.urihttp://hdl.handle.net/10220/46835en
dc.description.abstractModern processor technologies have driven new designs and implementations in main-memory hash joins. Recently, Intel Many Integrated Core (MIC) co-processors (commonly known as Xeon Phi) embrace emerging x86 single-chip many-core techniques. Compared with contemporary multi-core CPUs, Xeon Phi has quite different architectural features: wider SIMD instructions, many cores and hardware contexts, as well as lower-frequency in-order cores. In this paper, we experimentally revisit the state-of-the-art hash join algorithms on Xeon Phi co-processors. In particular, we study two camps of hash join algorithms: hardware-conscious ones that advocate careful tailoring of the join algorithms to underlying hardware architectures and hardware-oblivious ones that omit such careful tailoring. For each camp, we study the impact of architectural features and software optimizations on Xeon Phi in comparison with results on multi-core CPUs. Our experiments show two major findings on Xeon Phi, which are quantitatively different from those on multi-core CPUs. First, the impact of architectural features and software optimizations has quite different behavior on Xeon Phi in comparison with those on the CPU, which calls for new optimization and tuning on Xeon Phi. Second, hardware oblivious algorithms can outperform hardware conscious algorithms on a wide parameter window. These two findings further shed light on the design and implementation of query processing on new-generation single-chip many-core technologies.en
dc.description.sponsorshipASTAR (Agency for Sci., Tech. and Research, S’pore)en
dc.description.sponsorshipMOE (Min. of Education, S’pore)en
dc.format.extent12 p.en
dc.language.isoenen
dc.relation.ispartofseriesProceedings of the VLDB Endowmenten
dc.rights© 2015 The VLDB Endowment. This work is licensed under the Creative Commons AttributionNonCommercial-NoDerivs 3.0 Unported License. To view a copy of this license, visit http://creativecommons.org/licenses/by-nc-nd/3.0/. Obtain permission prior to any use beyond those covered by the license. Contact copyright holder by emailing info@vldb.org. Articles from this volume were invited to present their results at the 41st International Conference on Very Large Data Bases, August 31st - September 4th 2015, Kohala Coast, Hawaii.en
dc.subjectDRNTU::Engineering::Computer science and engineeringen
dc.subjectMany Integrated Coreen
dc.subjectXeon Phien
dc.titleImproving main memory hash joins on Intel Xeon Phi processorsen
dc.typeJournal Articleen
dc.contributor.schoolSchool of Computer Science and Engineeringen
dc.contributor.schoolInterdisciplinary Graduate School (IGS)en
dc.contributor.researchNTU-UBC Research Centre of Excellence in Active Living for the Elderlyen
dc.identifier.doi10.14778/2735703.2735704en
dc.description.versionPublished versionen
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