Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/88764
Title: Extensive Laser Fault Injection Profiling of 65 nm FPGA
Authors: Breier, Jakub
He, Wei
Bhasin, Shivam
Jap, Dirmanto
Chef, Samuel
Ong, Hock Guan
Gan, Chee Lip
Keywords: Cryptographic Fault Attack
Laser Fault Injection
Issue Date: 2017
Source: Breier, J., He, W., Bhasin, S., Jap, D., Chef, S., Ong, H. G., et al. (2017). Extensive Laser Fault Injection Profiling of 65 nm FPGA. Journal of Hardware and Systems Security, 1(3), 237-251.
Series/Report no.: Journal of Hardware and Systems Security
Abstract: Fault injection attacks have been widely investigated in both academia and industry during the past decade. In this attack approach, the adversary intentionally induces computational faults in the security components of the integrated circuit (IC) for deducing the confidential information processed or stored inside the device. However, the internal architecture of real-world devices is typically unknown to the attacker and the insufficient information about the device internals often cannot satisfy requirements of a practical fault injection attack. In this paper, we target Field Programmable Gate Array (FPGA) that is widely used in hardware security applications. By analyzing the faulty outputs of implemented algorithms, the scale of logic arrays and the sensitive logic cells can be precisely profiled. Using the outcome of this work, practical attacks can be significantly accelerated, without a need of time-consuming chip-scale injection scan. In addition, the observed fault models are compatible with most of the previously proposed fault models for differential or algebraic fault attacks (DFA/AFA). Moreover, a low-cost and highly sensitive logic-level countermeasure for predicting the laser fault injection attempt is described, which can be applied into any digital IC with a minimal overhead.
URI: https://hdl.handle.net/10356/88764
http://hdl.handle.net/10220/44737
ISSN: 2509-3428
DOI: 10.1007/s41635-017-0016-z
Rights: © 2017 Springer International Publishing AG. This is the author created version of a work that has been peer reviewed and accepted for publication by Journal of Hardware and Systems Security, Springer International Publishing AG. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [http://dx.doi.org/10.1007/s41635-017-0016-z].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:MSE Journal Articles

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