Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/88777
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dc.contributor.authorBalasubramanian, Padmanabhanen
dc.contributor.authorMaskell, Douglasen
dc.contributor.authorMastorakis, Nikosen
dc.date.accessioned2018-12-14T04:04:34Zen
dc.date.accessioned2019-12-06T17:10:43Z-
dc.date.available2018-12-14T04:04:34Zen
dc.date.available2019-12-06T17:10:43Z-
dc.date.issued2018en
dc.identifier.citationBalasubramanian, P., Maskell, D., & Mastorakis, N. (2018). Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic. Electronics, 7(10), 243-. doi:10.3390/electronics7100243en
dc.identifier.urihttps://hdl.handle.net/10356/88777-
dc.description.abstractAdder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.en
dc.description.sponsorshipMOE (Min. of Education, S’pore)en
dc.format.extent21 p.en
dc.language.isoenen
dc.relation.ispartofseriesElectronicsen
dc.rights© 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).en
dc.subjectDRNTU::Engineering::Computer science and engineeringen
dc.subjectDigital Circuitsen
dc.subjectAsynchronous Designen
dc.titleLow power robust early output asynchronous block carry lookahead adder with redundant carry logicen
dc.typeJournal Articleen
dc.contributor.schoolSchool of Computer Science and Engineeringen
dc.identifier.doi10.3390/electronics7100243en
dc.description.versionPublished versionen
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