Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/90051
Full metadata record
DC FieldValueLanguage
dc.contributor.authorMastorakis, N. E.en
dc.contributor.authorBalasubramanian, Padmanabhanen
dc.contributor.authorMaskell, Douglas Leslieen
dc.contributor.editorMa, Junen
dc.date.accessioned2019-07-17T02:38:24Zen
dc.date.accessioned2019-12-06T17:39:36Z-
dc.date.available2019-07-17T02:38:24Zen
dc.date.available2019-12-06T17:39:36Z-
dc.date.issued2019en
dc.identifier.citationBalasubramanian, P., Maskell, D. L., & Mastorakis, N. E. (2019). Speed and energy optimized quasi-delay-insensitive block carry lookahead adder. PLoS ONE, 14(6), e0218347-. doi:10.1371/journal.pone.0218347en
dc.identifier.urihttps://hdl.handle.net/10356/90051-
dc.description.abstractWe present a new asynchronous quasi-delay-insensitive (QDI) block carry lookahead adder with redundant carry (BCLARC) realized using delay-insensitive dual-rail data encoding and 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking. The proposed QDI BCLARC is found to be faster and energy-efficient than the existing asynchronous adders which are QDI and non-QDI (i.e., relative-timed). Compared to existing asynchronous adders corresponding to various architectures such as the ripple carry adder (RCA), the conventional carry lookahead adder (CCLA), the carry select adder (CSLA), the BCLARC, and the hybrid BCLARC-RCA, the proposed BCLARC is found to be faster and more energy-optimized. The cycle time (CT), which is expressed as the sum of the worst-case times taken for processing the data and the spacer, governs the speed. The product of average power dissipation and CT viz. the power-cycle time product (PCTP) defines the low power/energy efficiency. For a 32-bit addition, the proposed QDI BCLARC achieves the following reductions in design metrics on average over its counterparts when considering RTZ and RTO handshaking: i) 20.5% and 19.6% reductions in CT and PCTP respectively compared to an optimum QDI early output RCA, ii) 16.5% and 15.8% reductions in CT and PCTP respectively compared to an optimum relative-timed RCA, iii) 32.9% and 35.9% reductions in CT and PCTP respectively compared to an optimum uniform input-partitioned QDI early output CSLA, iv) 47.5% and 47.2% reductions in CT and PCTP respectively compared to an optimum QDI early output CCLA, v) 14.2% and 27.3% reductions in CT and PCTP respectively compared to an optimum QDI early output BCLARC, and vi) 12.2% and 11.6% reductions in CT and PCTP respectively compared to an optimum QDI early output hybrid BCLARC-RCA. The adders were implemented using a 32/28nm CMOS technology.en
dc.description.sponsorshipMOE (Min. of Education, S’pore)en
dc.format.extent27 p.en
dc.language.isoenen
dc.relation.ispartofseriesPLoS ONEen
dc.rights© 2019 Balasubramanian et al. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.en
dc.subjectEngineering::Computer science and engineeringen
dc.subjectLogic Circuitsen
dc.subjectData Processingen
dc.titleSpeed and energy optimized quasi-delay-insensitive block carry lookahead adderen
dc.typeJournal Articleen
dc.contributor.schoolSchool of Computer Science and Engineeringen
dc.identifier.doi10.1371/journal.pone.0218347en
dc.description.versionPublished versionen
item.grantfulltextopen-
item.fulltextWith Fulltext-
Appears in Collections:SCSE Journal Articles
Files in This Item:
File Description SizeFormat 
Speed and energy optimized quasi-delay-insensitive block carry lookahead adder.pdf2.45 MBAdobe PDFThumbnail
View/Open

SCOPUSTM   
Citations 50

1
Updated on Jul 6, 2022

PublonsTM
Citations 20

3
Updated on Jul 6, 2022

Page view(s)

185
Updated on Aug 9, 2022

Download(s) 50

35
Updated on Aug 9, 2022

Google ScholarTM

Check

Altmetric


Plumx

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.