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dc.contributor.authorLi, Mengquanen
dc.contributor.authorLiu, Weichenen
dc.contributor.authorYang, Leien
dc.contributor.authorChen, Pengen
dc.contributor.authorChen, Chaoen
dc.identifier.citationLi, M., Liu, W., Yang, L., Chen, P., & Chen, C. (2018). Chip temperature optimization for dark silicon many-core systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(5), 941-953. doi:10.1109/TCAD.2017.2740306en
dc.description.abstractIn the dark silicon era, a fundamental problem is given a real-time computation demand, how to determine if an on-chip multiprocessor system is able to accept this demand and to maintain its reliability by keeping every core within a safe temperature range. In this paper, a practical thermal model is described for quick chip temperature prediction. Integrated with the thermal model, we present a mixed integer linear programming (MILP) model to find the optimal task-to-core assignment with the minimum chip peak temperature. For the worst case where even the minimum chip peak temperature exceeds the safe temperature, a heuristic algorithm, called temperature-constrained task selection (TCTS), is proposed to optimize the system performance within chip safe temperature. The optimality of the TCTS algorithm is formally proven. Extensive performance evaluations show that our thermal model achieves an average prediction accuracy of 0.0741 °C within 0.2392 ms. The MILP model reduces chip peak temperature of ~10 °C comparing with traditional techniques. The system performance is increased by 19.8% under safe temperature limitation. Due to the satisfying scalability of our MILP formulation, the chip peak temperature is further decreased by 5.06 °C via the TCTS algorithm. The feasibility of this systematical technique is testified in a real case study as well.en
dc.format.extent13 p.en
dc.relation.ispartofseriesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systemsen
dc.rights© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at:
dc.subjectDark Siliconen
dc.subjectChip Temperature Optimizationen
dc.subjectDRNTU::Engineering::Computer science and engineeringen
dc.titleChip temperature optimization for dark silicon many-core systemsen
dc.typeJournal Articleen
dc.contributor.schoolSchool of Computer Science and Engineeringen
dc.description.versionAccepted versionen
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