Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/90107
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dc.contributor.authorLiu, Weichenen
dc.contributor.authorYang, Leien
dc.contributor.authorJiang, Weiwenen
dc.contributor.authorFeng, Liangen
dc.contributor.authorGuan, Nanen
dc.contributor.authorZhang, Weien
dc.contributor.authorDutt, Nikilen
dc.date.accessioned2019-05-27T04:02:14Zen
dc.date.accessioned2019-12-06T17:40:49Z-
dc.date.available2019-05-27T04:02:14Zen
dc.date.available2019-12-06T17:40:49Z-
dc.date.issued2018en
dc.identifier.citationLiu, W., Yang, L., Jiang, W., Feng, L., Guan, N., Zhang, W., & Dutt, N. (2018). Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip. IEEE Transactions on Computers, 67(12), 1818-1834. doi:10.1109/TC.2018.2844365en
dc.identifier.issn0018-9340en
dc.identifier.urihttps://hdl.handle.net/10356/90107-
dc.identifier.urihttp://hdl.handle.net/10220/48373en
dc.description.abstractDark silicon is the phenomenon that a fraction of many-core chip has to be turned off or run in a low-power state in order to maintain the safe chip temperature. System-level thermal management techniques normally map application on non-adjacent cores, while communication efficiency among these cores will be oppositely affected over conventional network-on-chip (NoC). Recently, SMART NoC architecture is proposed, enabling single-cycle multi-hop bypass channels to be built between distant cores at runtime, to reduce communication latency. However, communication efficiency of SMART NoC will be diminished by communication contention, which will in turn decrease system performance. In this paper, we first propose an Integer-Linear Programming (ILP) model to properly address communication problem, which generates the optimal solutions with the consideration of inter-processor communication. We further present a novel heuristic algorithm for task mapping in dark silicon many-core systems, called TopoMap, on top of SMART architecture, which can effectively solve communication contention problem in polynomial time. With fine-grained consideration of chip thermal reliability and inter-processor communication, presented approaches are able to control the reconfigurability of NoC communication topology in task mapping and scheduling. Thermal-safe system is guaranteed by physically decentralized active cores, and communication overhead is reduced by the minimized communication contention and maximized bypass routing. Performance evaluation on PARSEC shows the applicability and effectiveness of the proposed techniques, which achieve on average 42.5 and 32.4 percent improvement in communication and application performance, and 32.3 percent reduction in system energy consumption, compared with state-of-the-art techniques. TopoMap only introduces 1.8 percent performance difference compared to ILP model and is more scalable to large-size NoCs.en
dc.format.extent16 p.en
dc.language.isoenen
dc.relation.ispartofseriesIEEE Transactions on Computersen
dc.rights© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TC.2018.2844365.en
dc.subjectReconfigurable NoCen
dc.subjectTask Mappingen
dc.subjectDRNTU::Engineering::Computer science and engineeringen
dc.titleThermal-aware task mapping on dynamically reconfigurable network-on-chip based multiprocessor system-on-chipen
dc.typeJournal Articleen
dc.contributor.schoolSchool of Computer Science and Engineeringen
dc.identifier.doi10.1109/TC.2018.2844365en
dc.description.versionAccepted versionen
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