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|Title:||All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits||Authors:||Park, Gyusung
Kim, Chris H.
|Keywords:||DRNTU::Engineering::Electrical and electronic engineering
Bias Temperature Instability
Hot Carrier Injection
|Issue Date:||2018||Source:||Park, G., Kim, M., Kim, C. H., Kim, B., & Reddy, V. (2018). All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits. 2018 IEEE International Reliability Physics Symposium (IRPS), 5C.21-5C.26. doi:10.1109/IRPS.2018.8353613||Abstract:||Using simple on-chip monitoring circuits, we precisely characterized the impact of hot carrier injection and bias temperature instability on frequency and phase noise degradation of a 65nm all-digital PLL circuit. Experimental data shows that PLL phase noise degrades with aging even though the output frequency is maintained constant due to the PLL feedback operation. Results show that applying high temperature annealing can recover most of the phase noise degradation.||URI:||https://hdl.handle.net/10356/90235
|DOI:||10.1109/IRPS.2018.8353613||Rights:||© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/IRPS.2018.8353613||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Conference Papers|
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