Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/90557
Title: An ultra low-power successive approximation ADC using an offset-biased auto-zero comparator
Authors: Chan, Pak Kwong
Susanti, Yulia
Ong, Vincent K. S.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2008
Source: Chan, P. K., Susanti, Y., & Ong, V. K. S. (2009). An ultra low-power successive approximation ADC using an offset-biased auto-zero comparator. In proceedings of the 9th IEEE Asia Pacific Conference on Circuits and Systems: Macau, (pp.284-287).
Abstract: This paper presents a new offset-biased autozero comparator for the design of an ultra low-power charge redistribution Successive Approximation Analogto- Digital Converter (SA-ADC) dedicated to biomedical applications. The circuits are realized in CSM 0.18μm CMOS technology. The simulated results have shown that the power consumption of the 10-bit ADC is only 6.2μW at a single supply of 1.8V whilst sampling at a frequency of 64kHz, with conversion time of 187.5μs. The energy per quantization level is less than 0.1pJ/level.
URI: https://hdl.handle.net/10356/90557
http://hdl.handle.net/10220/6377
DOI: 10.1109/APCCAS.2008.4746015
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Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Conference Papers

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