Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/90594
Title: High-speed and low-power serial accumulator for serial/parallel multiplier
Authors: Meher, Manas Ranjan
Jong, Ching Chuen
Chang, Chip Hong
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2008
Source: Meher, M. R., Jong, C. C., & Chang, C. H. (2008). High-speed and low-power serial accumulator for serial/parallel multiplier. IEEE Asia Pacific Conference on Circuits and Systems, pp.176-179, Macau, China.
Abstract: This paper presents a new approach to serial/parallel multiplier design by using parallel 1's counters to accumulate the binary partial product bits. The 1's in each column of the partial product matrix due to the serially input operands are accumulated using a serial T-flip flop (TFF) counter. Consequently, the column height is reduced from N to [log2 N]+1. This logarithmic reduction results in a very small carry save adder (CSA) array or tree required before the two final summands are added up to obtain the final product. The counters can be clocked at very high frequency (around 1.5 GHz as dictated mainly by the TFF propagation delay) and the accumulation frequency is independent of the operand size. The proposed accumulation method achieves 33%, 38%, 43% gain in speed respectively for 31, 63, 127 operands accumulators and on average 42% reduction in power consumption over CSA based accumulation implemented in 0.18 µm CMOS technology.
URI: https://hdl.handle.net/10356/90594
http://hdl.handle.net/10220/6353
DOI: 10.1109/APCCAS.2008.4745989
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Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Conference Papers

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