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|Title:||Nickel-silicided Schottky junction CMOS transistors with gate-all-around nanowire channels||Authors:||Tang, L. J.
Ho, C. K. F.
Tan, Eu Jin
Pey, Kin Leong
Chi, Dong Zhi
Chin, Yoke King
Lee, Pooi See
|Keywords:||DRNTU::Engineering::Materials||Issue Date:||2008||Source:||Tan, E. J., Pey, K. L., Singh, N., Lo, G. Q., Chi, D. Z., Chin, Y. K., et al. (2008). Nickel-silicided Schottky Junction CMOS Transistors with Gate-all-around Nanowire Channels. IEEE Electron Device Letters, 29(8), 902-905.||Series/Report no.:||IEEE electron device letters||Abstract:||We demonstrate high-performance Schottky CMOS transistors with NiSi source/drain and gate-all-around (GAA) silicon nanowire (~5 nm) channels. The transistors exhibit good Ion/Ioff characteristics, along with fully controlled shortchannel effects revealed by low drain-induced barrier lowering (~10 mV/V) and near-ideal subthreshold swing (~60 mV/dec). Although the N-MOSFET required dopant segregation to suppress the ambipolar behavior, excellent P-MOSFET characteristics could be achieved without the use of barrier modification techniques. We attribute this to the Schottky barrier thinning in a nanosized metal–semiconductor junction and superior gate electrostatic control in a GAA nanowire architecture.||URI:||https://hdl.handle.net/10356/90670
|DOI:||10.1109/LED.2008.2000876||Rights:||© 2008 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: http://dx.doi.org/10.1109/LED.2008.2000876.||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||MSE Journal Articles|
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