Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/90676
Title: Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops
Authors: Phyu, Myint Wai
Fu, Kang Kang
Goh, Wang Ling
Yeo, Kiat Seng
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2009
Source: Phyu, M. W., Fu, K. K., Goh, W. L., & Yeo, K. S. (2009). Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1-9.
Series/Report no.: IEEE transactions on very large scale integration (VLSI) systems
Abstract: A novel explicit-pulsed dual-edge triggered sense-amplifier flip-flop (DET-SAFF) for low-power and high-performance applications is presented in this paper. By incorporating the dual-edge triggering mechanism in the new fast latch and employing conditional precharging, the DET-SAFF is able to achieve low-power consumption that has small delay. To further reduce the power consumption at low switching activities, a clock-gated sense-amplifier (CG-SAFF) is engaged. Extensive post-layout simulations proved that the proposed DET-SAFF exhibits both the low-power and high-speed properties, with delay and power reduction of up to 43.3% and 33.5% of those of the prior art, respectively. When the switching activity is less than 0.5, the proposed CG-SAFF demonstrates its superiority in terms of power reduction. During zero input switching activity, CG-SAFF can realize up to 86% in power saving. Lastly, a modification to the proposed circuit has led to an improved common-mode rejection ratio (CMRR) DET-SAFF.
URI: https://hdl.handle.net/10356/90676
http://hdl.handle.net/10220/6319
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2009.2029116
Rights: © 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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