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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Phyu, Myint Wai | en |
dc.contributor.author | Fu, Kang Kang | en |
dc.contributor.author | Goh, Wang Ling | en |
dc.contributor.author | Yeo, Kiat Seng | en |
dc.date.accessioned | 2010-08-19T00:45:47Z | en |
dc.date.accessioned | 2019-12-06T17:52:00Z | - |
dc.date.available | 2010-08-19T00:45:47Z | en |
dc.date.available | 2019-12-06T17:52:00Z | - |
dc.date.copyright | 2009 | en |
dc.date.issued | 2009 | en |
dc.identifier.citation | Phyu, M. W., Fu, K. K., Goh, W. L., & Yeo, K. S. (2009). Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1-9. | en |
dc.identifier.issn | 1063-8210 | en |
dc.identifier.uri | https://hdl.handle.net/10356/90676 | - |
dc.description.abstract | A novel explicit-pulsed dual-edge triggered sense-amplifier flip-flop (DET-SAFF) for low-power and high-performance applications is presented in this paper. By incorporating the dual-edge triggering mechanism in the new fast latch and employing conditional precharging, the DET-SAFF is able to achieve low-power consumption that has small delay. To further reduce the power consumption at low switching activities, a clock-gated sense-amplifier (CG-SAFF) is engaged. Extensive post-layout simulations proved that the proposed DET-SAFF exhibits both the low-power and high-speed properties, with delay and power reduction of up to 43.3% and 33.5% of those of the prior art, respectively. When the switching activity is less than 0.5, the proposed CG-SAFF demonstrates its superiority in terms of power reduction. During zero input switching activity, CG-SAFF can realize up to 86% in power saving. Lastly, a modification to the proposed circuit has led to an improved common-mode rejection ratio (CMRR) DET-SAFF. | en |
dc.format.extent | 9 p. | en |
dc.language.iso | en | en |
dc.relation.ispartofseries | IEEE transactions on very large scale integration (VLSI) systems | en |
dc.rights | © 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. | en |
dc.subject | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits | en |
dc.title | Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops | en |
dc.type | Journal Article | en |
dc.contributor.school | School of Electrical and Electronic Engineering | en |
dc.identifier.doi | 10.1109/TVLSI.2009.2029116 | en |
dc.description.version | Published version | en |
item.fulltext | With Fulltext | - |
item.grantfulltext | open | - |
Appears in Collections: | EEE Journal Articles |
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File | Description | Size | Format | |
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Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops.pdf | 611.34 kB | Adobe PDF | View/Open |
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