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https://hdl.handle.net/10356/90768| Title: | FPGA implementation of digital filters synthesized using the frequency-response masking technique | Authors: | Zheng, H. Q. Lim, Yong Ching Yu, Ya Jun Foo, Say Wei |
Issue Date: | 2001 | Source: | Lim, Y. C., Yu, Y. J., Zheng, H.Q., & Foo, S.W. (2001). FPGA implementation of digital filters synthesized using the frequency-response masking technique. IEEE International Symposium on Circuits and Systems 2001: (pp. 173-176). Singapore: National University of Singapore. | Conference: | IEEE International Symposium on Circuits and Systems (2001 : Sydney, Australia) | Abstract: | The effective length of a filter designed using the frequency-response masking technique is very high and requires a very large number of delay elements. In this paper, we present some useful techniques for reducing the data transfer between the FPGA and external memory when the random logic are implemented using FPGA and the delay elements are implemented using external memory such as DRAM. | URI: | https://hdl.handle.net/10356/90768 http://hdl.handle.net/10220/4589 |
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| Appears in Collections: | EEE Conference Papers |
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| File | Description | Size | Format | |
|---|---|---|---|---|
| C41-II_173ISCAS2001LimYC.pdf | Accepted version | 51.19 kB | Adobe PDF |  View/Open |
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