Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/91586
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dc.contributor.authorGwee, Bah Hweeen
dc.contributor.authorChang, Joseph Sylvesteren
dc.contributor.authorShi, Yiqiongen
dc.contributor.authorChua, Chien Chungen
dc.contributor.authorChong, Kwen-Siongen
dc.date.accessioned2010-04-09T08:20:38Zen
dc.date.accessioned2019-12-06T18:08:23Z-
dc.date.available2010-04-09T08:20:38Zen
dc.date.available2019-12-06T18:08:23Z-
dc.date.copyright2009en
dc.date.issued2009en
dc.identifier.citationGwee, B. H., Chang, J. S., Shi, Y., Chua, C. C., & Chong, K. S. (2009). A low-voltage micropower asynchronous multiplier with shift-add multiplication approach. IEEE Transactions on Circuits and Systems I, 56 (7), 1349-1359.en
dc.identifier.issn1549-8328en
dc.identifier.urihttps://hdl.handle.net/10356/91586-
dc.identifier.urihttp://hdl.handle.net/10220/6227en
dc.description.abstractThe design of a low-voltage micropower asynchronous (async) signed truncated multiplier based on a shift–add structure for power-critical applications such as the low-clock-rate ( 4 MHz) hearing aids is described. The emphases of the design are micropower operation and small IC area, and these attributes are achieved in several ways. First, a maximum of three signed power-of-two terms accompanied with sign magnitude data representation is used for the multiplier operand. Second, the least significant partial products are truncated to yield a 16-bit signed product. An error correction methodology is proposed to mitigate, where appropriate, the arising truncation errors. The errors arising from truncation and the effectiveness of the error correction are analytically derived. Third, a low-power shifter design and an internal latch adder are adopted. Finally, a power-efficient speculative delay line is proposed to time the async operation of the various circuit modules. A comparison with competing synchronous and async designs shows that the proposed design features the lowest power dissipation (5.86 W at 1.1 V and 1 MHz) and a very competitive IC area (0.08 mm² using a 0.35-µm CMOS process). The application of the proposed multiplier for realizing a digital filter for a hearing aid is given.en
dc.format.extent12 p.en
dc.language.isoenen
dc.relation.ispartofseriesIEEE transactions on circuits and systems Ien
dc.rights© 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.en
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen
dc.titleA low-voltage micropower asynchronous multiplier with shift-add multiplication approachen
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.identifier.doihttp://dx.doi.org/10.1109/TCSI.2008.2006649en
dc.description.versionPublished versionen
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