Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/91597
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dc.contributor.authorChang, Joseph Sylvesteren
dc.contributor.authorTan, Meng Tongen
dc.contributor.authorCheng, Zhihongen
dc.contributor.authorTong, Yit Chowen
dc.date.accessioned2009-06-23T05:52:54Zen
dc.date.accessioned2019-12-06T18:08:37Z-
dc.date.available2009-06-23T05:52:54Zen
dc.date.available2019-12-06T18:08:37Z-
dc.date.copyright2000en
dc.date.issued2000en
dc.identifier.citationChang, J. S., Tan, M. T., Cheng, Z., & Tong, Y. C. (2000). Analysis and design of power efficient class D amplifier output stages. IEEE Transactions on Circuits and System-I: Fundamental Theory and Applications, 47(6), 897-902.en
dc.identifier.issn1057-7122en
dc.identifier.urihttps://hdl.handle.net/10356/91597-
dc.description.abstractA Class D amplifier comprises a pulse width modulator and an output stage. In this paper, we analyze the power dissipation mechanisms and derive the overall power efficiency of the output stage realized using the finger and waffle layouts.We compare the relative merits of these layouts. We propose two design methodologies to determine the aspect ratios of the transistors in the output stage for optimum power efficiency (optimum for a given fabrication process, supply voltage and load resistance): 1) optimization to a single modulation index point and 2) optimization to a range of modulation indexes. For the design of an output stage with optimum power efficiency (and small IC area), we recommend optimization to a range of modulation indexes and a layout realized by the waffle structure. The theoretical analysis and derivations are verified on the basis of computer simulations and measurements on fabricated prototype IC’s.en
dc.format.extent6 p.en
dc.language.isoenen
dc.relation.ispartofseriesIEEE transactions on circuits and system-I : fundamental theory and applicationsen
dc.rights© 2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site.en
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen
dc.titleAnalysis and design of power efficient class D amplifier output stagesen
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.identifier.doi10.1109/81.852942en
dc.description.versionPublished versionen
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