Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/91615
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dc.contributor.authorRofail, Samir S.en
dc.contributor.authorYeo, Kiat Sengen
dc.date.accessioned2009-08-03T04:29:03Zen
dc.date.accessioned2019-12-06T18:08:58Z-
dc.date.available2009-08-03T04:29:03Zen
dc.date.available2019-12-06T18:08:58Z-
dc.date.copyright1998en
dc.date.issued1998en
dc.identifier.citationYeo, K. S., & Samir, S. R. (1998). A charge-trapping-based technique to design low-voltage BiCMOS logic circuits. IEEE Journal of Solid-State Circuits, 33(1), 164-168.en
dc.identifier.issn0018-9200en
dc.identifier.urihttps://hdl.handle.net/10356/91615-
dc.description.abstractNew BiCMOS logic circuits employing a charge trapping technique are presented. The circuits include an XOR gate and an adder. Submicrometer technologies are used in the simulation and the circuits’ performances are comparatively evaluated with the CMOS and that of the recently reported circuits. The proposed circuits were fabricated using a standard 0.8-µm BiCMOS process. The experimental results obtained from the fabricated chip have verified the functionality of the proposed logic gates.en
dc.format.extent5 p.en
dc.language.isoenen
dc.relation.ispartofseriesIEEE journal of solid-state circuitsen
dc.rightsIEEE Journal of Solid-State Circuits © 1998 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site.en
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen
dc.titleA charge-trapping-based technique to design low-voltage BiCMOS logic circuitsen
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.identifier.doi10.1109/4.654950en
dc.description.versionPublished versionen
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