Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/91616
Title: An area efficient high turn ratio monolithic transformer for silicon RFIC
Authors: Lim, Chee Chong
Yeo, Kiat Seng
Chew, Kok Wai Johnny
Lim, Suh Fei
Boon, Chirn Chye
Qiu, Ping
Do, Manh Anh
Chan, Lap
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 2008
Source: Lim, C. C., Yeo K. S., Chew, K. W., Lim, S. F., Boon, C. C., Qiu, P., et al. (2008). An area efficient high turn ratio monolithic transformer for silicon RFIC. IEEE Radio Frequency Integrated Circuits Symposium: Atlanta,GA,USA, (pp.167-170).
Abstract: A novel way of manufacturing an on-chip transformer that produces high inductance ratio (LSec/LPri > 30) with excellent area efficiency is presented. This technique uses an electrical all-round coupling effect of a conductor A (Primary Coil), having large effective width, and a densely routed conductor B (Secondary Coil). Thus, a high turn ratio monolithic transformer, using minimum die size, is realizable on silicon. The coil having the dense routing can also be doubled up as a monolithic RF choke on silicon. In this work, area efficiency is compared between various type of existing transformer structures (i.e. Interleaved and Stacked transformer), based on unit inductance. The method presented is fully compatible to all the foundry standard CMOS processes.
URI: https://hdl.handle.net/10356/91616
http://hdl.handle.net/10220/6381
DOI: 10.1109/RFIC.2008.4561410
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Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Conference Papers

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