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https://hdl.handle.net/10356/91707| Title: | A time-multiplexed switched-capacitor CDS equalizer with reduced crosstalk layout | Authors: | Ng, K. A. Chan, Pak Kwong |
Keywords: | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits | Issue Date: | 2005 | Source: | Ng, K. A., & Chan, P. K., (2005). A time-multiplexed switched-capacitor CDS equalizer with reduced crosstalk layout. IEEE Transactions on Circuits and Systems, 52(10), 2065-2074. | Series/Report no.: | IEEE transactions on circuits and systems | Abstract: | A new time-multiplexed switched-capacitor (TM-SC)equalizer is designed on the basis of the previously reported correlated double-sampling integrator and the crosstalk reduction layout approach, which aims at improving the performance aspects on crosstalk, gain loss, 1 noise and offset. The equalizer, which operates at a single 3-V supply and has a filter bank with 4 TM channels, has been fabricated to confirm the effectiveness of the structure using a standard 0.8- m CMOS process. Index Terms—Crosstalk, equalizers, integrated circuit, layout, switched-capacitor (SC) circuit, time-multiplexed (TM) circuit. | URI: | https://hdl.handle.net/10356/91707 http://hdl.handle.net/10220/4561 |
ISSN: | 0098-4094 | DOI: | 10.1109/TCSI.2005.852921 | Rights: | IEEE Transactions on Circuits and Systems. © 2006 IEEE. Journal can be found at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=31. | Fulltext Permission: | open | Fulltext Availability: | With Fulltext |
| Appears in Collections: | EEE Journal Articles |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| A Time-Multiplexed Switched-Capacitor CDS Equalizer with Reduced Crosstalk Layout .pdf | Published version | 954 kB | Adobe PDF |  View/Open |
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