Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/92303
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dc.contributor.authorTheng, A. L.en
dc.contributor.authorGoh, Wang Lingen
dc.contributor.authorNg, C. M.en
dc.contributor.authorChan, L.en
dc.contributor.authorLo, Guo-Qiangen
dc.date.accessioned2010-05-05T06:40:42Zen
dc.date.accessioned2019-12-06T18:21:01Z-
dc.date.available2010-05-05T06:40:42Zen
dc.date.available2019-12-06T18:21:01Z-
dc.date.copyright2008en
dc.date.issued2008en
dc.identifier.citationTheng, A. L., Goh, W. L., Ng, C. M., Chan, L. & Lo, G. Q. (2008). Dual Nanowire Silicon MOSFET with Silicon Bridge and TaN Gate. IEEE Transactions on Nanotechnology. 7(6), 795-799.en
dc.identifier.issn1536-125Xen
dc.identifier.urihttps://hdl.handle.net/10356/92303-
dc.description.abstractThis paper demonstrates a high performance silicon nanowire mosfet built on silicon-on-insulator (SOI) platform. Stress-limiting oxidation technique was exploited for dual nanowire channel formation. To further improve the performance of the device, TaN metal gate is used instead of the conventional polysilicon gate. The thin silicon bridge between the two nanowires provides a small boost in the drive current, without degrading the short channel performance. The novel structures are able to achieve excellent electrical performances, high drive current of 927 μA/μm for p-channel and 554 μA/μm for n-channel, near ideal subthreshold slope (SS), and low drain-induced barrier lowering (DIBL).en
dc.format.extent5 p.en
dc.language.isoenen
dc.relation.ispartofseriesIEEE transactions on nanotechnologyen
dc.rights© 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.en
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen
dc.titleDual nanowire silicon MOSFET with silicon bridge and TaN gateen
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.identifier.doi10.1109/TNANO.2008.917845en
dc.description.versionPublished versionen
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