Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/92314
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dc.contributor.authorZhang, Yue Pingen
dc.contributor.authorYang, Kaien
dc.contributor.authorYin, Wen Yanen
dc.contributor.authorShi, Jinglinen
dc.contributor.authorKang, Kaien
dc.contributor.authorMao, Jun Faen
dc.date.accessioned2010-05-05T06:50:42Zen
dc.date.accessioned2019-12-06T18:21:12Z-
dc.date.available2010-05-05T06:50:42Zen
dc.date.available2019-12-06T18:21:12Z-
dc.date.copyright2008en
dc.date.issued2008en
dc.identifier.citationYang, K., Yin, W. Y., Shi, J., Kang, K., Mao, J. F., & Zhang, Y. P. (2008). Study of On-Chip Stacked Multiloop Spiral Inductors. IEEE Transactions on Electron Devices. 55(11), 3236-3245.en
dc.identifier.issn0018-9383en
dc.identifier.urihttps://hdl.handle.net/10356/92314-
dc.description.abstractThis paper proposes a new differential topology that features a stacked multiloop inductor. Comparative studies of stacked one- to four-loop spiral inductors with and without patterned ground shields (PGSs) for silicon-based radio-frequency integrated circuits (RFICs) were conducted, and lumped-element circuit models were developed for these inductors. The partialelement equivalent-circuit method that can accurately analyze mutual inductive couplings among different spirals in these multiloop geometries was employed for capturing the frequency dependent inductances and resistances of inductors at low frequencies. A good agreement between numerical results and measurements is obtained. It is demonstrated that a stacked multiloop spiral inductor with differential topology and PGS has a larger inductance and a higher Q-factor as compared with the same inductor without differential topology and PGS. This hybrid methodology could provide a promising technique for developing new silicon-based passive devices used in RFICs.en
dc.format.extent10 p.en
dc.language.isoenen
dc.relation.ispartofseriesIEEE transactions on electron devicesen
dc.rights© 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.en
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen
dc.titleA study of on-chip stacked multi-loop spiral inductorsen
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.identifier.doi10.1109/TED.2008.2004648en
dc.description.versionPublished versionen
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