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Title: A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle operation for medical imaging applications
Authors: Sunny, Sharma
Chen, Yong
Boon, Chirn Chye
Keywords: 1.5-bit/cycle
Engineering::Electrical and electronic engineering
Issue Date: 2018
Source: Sunny, S., Chen, Y., & Boon, C. C. (2018). A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle operation for medical imaging applications. IEEE Sensors Journal, 18(11), 4553-4560. doi:10.1109/JSEN.2018.2825400
Series/Report no.: IEEE Sensors Journal
Abstract: This paper reports a 10-bit 150 MS/s successive approximation register analog-to-digital converter with binary-scaled redundancy-facilitated error correction technique. The proposed 1.5-bit/cycle technique with built-in capacitive digital-to-analog converter (CDAC) redundancy, corrects multiple erroneous decisions in a total of nine conversion cycles. The proposed binary-scaled redundancy provides a 12.5% error tolerance range for the incomplete CDAC voltage settling. The digital error-correction logic circuit presented uses a bit-overlap-and-add technique. The prototype chip was fabricated in 65-nm CMOS technology and occupies chip area of 0.038 mm 2 . It consumes 4.06 mW from a 1.2 V supply, achieving the Nyquist signal-to-noise-and-distortion ratio of 57.81 dB and the effective number of bits of 9.31-bit at an operating frequency of 150 MS/s, corresponding to the figure-of-merit of 42.6 fJ/ conversion-step.
ISSN: 1530-437X
DOI: 10.1109/JSEN.2018.2825400
Rights: © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at:
Fulltext Permission: open
Fulltext Availability: With Fulltext
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