Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/92667
Title: A capacitive-based accelerometer IC using injection-nulling switch technique
Authors: Lee, W. F.
Chan, Pak Kwong
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2008
Source: Lee, W. F., & Chan, P. K. (2008). A Capacitive-Based Accelerometer IC using Injection-Nulling Switch Technique. IEEE Transactions on Circuits and Systems—I. 55(4), 980-989.
Series/Report no.: IEEE transactions on circuits and systems—I
Abstract: This paper presents a new fully integrated sensing interface and signal-conditioning application-specific integrated circuit (ASIC) for automotive accelerometers based on an "injection-nulling switch" (INS) technique. The INS technique simplifies the design of both the switched-capacitor (SC) sensing amplifier and its supporting building blocks without jeopardizing its performance. This is done by counteracting the impact of charge injection and clock-feedthrough effects on sensitivity, resolution, and offset. It also decreases the number of opamps, capacitors, and switches being used. This results in reduction of power consumption, potential switching noise, and noise (sampled thermal noise which increases with the number of SC pairs being used) in the ASIC. A two-chip approach has been adopted in the implementation, with sensing element and ASIC. The built-in trimming circuitry and signal-conditioning blocks, which includes a self-test circuit, are implemented internally to eliminate the need for external components. The experimental results have shown that the sensing system IC has achieved a power consumption of 10 mW (2 mA at 5 V), a maximum noise root spectral density of 11.87 µVpk/√Hz equivalent to rms noise root spectral density of 0.187mg/√Hz at 15.63 Hz, a signal-to-noise dynamic range of 77dB for 500-Hz bandwidth and 74 dB for 1-kHz bandwidth based on 50 g, and a maximum clock noise of 1.562 mV. The die size of the ASIC is 2.8 mm x 2.3 mm using a standard 0.6-µm CMOS technology.
URI: https://hdl.handle.net/10356/92667
http://hdl.handle.net/10220/6274
ISSN: 1549-8328
DOI: 10.1109/TCSI.2008.916557
Rights: © 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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