Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/93565
Title: Design and performance evaluation of a low-power data-line SRAM sense amplifier
Authors: Fu, Haitao
Yeo, Kiat Seng
Do, Anh Tuan
Kong, Zhi Hui
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2009
Source: Fu, H., Yeo, K. S., Do, A. T., & Kong, Z. H. (2009). Design and performance evaluation of a low-power data-line SRAM sense amplifier. Proceedings of the 2009 12th International Symposium on Integrated Circuits (pp. 291-294), Singapore.
Abstract: The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. The heavy bitand data-line capacitances are the major road blocks to its performance. A high-performance SRAM is proposed using a 1.8 V/0.18 μm CMOS standard process from Chartered Semiconductor Manufacturing Ltd (CHRT). It incorporates a discharging mechanism that helps eliminating the waiting time during the read operation, hence offering a faster sensing speed and lower power consumption. Our post-layout simulation results have shown that it improves the sensing speed and power consumption by 51.4%, and 62.47%, respectively when compared with the best published design. The total Power-Delay-Product (PDP) is 81.79% better. Furthermore, it can operate at a supply voltage as low as 0.8 V with a high stability to the bit-line capacitances variation and mismatch.
URI: https://hdl.handle.net/10356/93565
http://hdl.handle.net/10220/6348
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Appears in Collections:EEE Conference Papers

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