Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/93565
Title: Design and performance evaluation of a low-power data-line SRAM sense amplifier
Authors: Fu, Haitao
Yeo, Kiat Seng
Do, Anh Tuan
Kong, Zhi Hui
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2009
Source: Fu, H., Yeo, K. S., Do, A. T., & Kong, Z. H. (2009). Design and performance evaluation of a low-power data-line SRAM sense amplifier. Proceedings of the 2009 12th International Symposium on Integrated Circuits (pp. 291-294), Singapore.
Conference: IEEE International Symposium on Integrated Circuits (12th : 2009 : Singapore)
Abstract: The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. The heavy bitand data-line capacitances are the major road blocks to its performance. A high-performance SRAM is proposed using a 1.8 V/0.18 μm CMOS standard process from Chartered Semiconductor Manufacturing Ltd (CHRT). It incorporates a discharging mechanism that helps eliminating the waiting time during the read operation, hence offering a faster sensing speed and lower power consumption. Our post-layout simulation results have shown that it improves the sensing speed and power consumption by 51.4%, and 62.47%, respectively when compared with the best published design. The total Power-Delay-Product (PDP) is 81.79% better. Furthermore, it can operate at a supply voltage as low as 0.8 V with a high stability to the bit-line capacitances variation and mismatch.
URI: https://hdl.handle.net/10356/93565
http://hdl.handle.net/10220/6348
Schools: School of Electrical and Electronic Engineering 
Rights: © 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Conference Papers

Files in This Item:
File Description SizeFormat 
Design and Performance Evaluation of a Low-power Data-line SRAM Sense Amplifier.pdf377.25 kBAdobe PDFThumbnail
View/Open

Page view(s) 5

956
Updated on Mar 27, 2024

Download(s) 10

389
Updated on Mar 27, 2024

Google ScholarTM

Check

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.