Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/94266
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dc.contributor.authorLwin, Z. Z.en
dc.contributor.authorPey, Kin Leongen
dc.contributor.authorZhang, Q.en
dc.contributor.authorBosman, Michelen
dc.contributor.authorLiu, Q.en
dc.contributor.authorGan, C. L.en
dc.contributor.authorSingh, P. K.en
dc.contributor.authorMahapatra, S.en
dc.date.accessioned2013-02-18T03:10:10Zen
dc.date.accessioned2019-12-06T18:53:31Z-
dc.date.available2013-02-18T03:10:10Zen
dc.date.available2019-12-06T18:53:31Z-
dc.date.copyright2012en
dc.date.issued2012en
dc.identifier.citationLwin, Z. Z., Pey, K. L., Zhang, Q., Bosman, M., Liu, Q., Gan, C. L., et al. (2012). Study of charge distribution and charge loss in dual-layer metal-nanocrystal-embedded high-κ/SiO2 gate stack. Applied Physics Letters, 100(19), 193109-.en
dc.identifier.issn0003-6951en
dc.identifier.urihttps://hdl.handle.net/10356/94266-
dc.description.abstractIn this work, we present a comprehensive experimental study of charge loss mechanisms in a dual-layer metal nanocrystal (DL-MNC) embedded high-κ/SiO2 gate stack. Kelvin force microscopy characterization reveals that the internal-electric-field assisted tunneling could be a dominant charge loss mechanism in DL devices that mainly depends on the charge distribution in two MNC-layers and inter-layer dielectric (ILD) thickness between the two layers of nanocrystals. Our findings suggest that an optimized DL-MNCs embedded memory cell could be achieved by defining the ILD thickness larger than the average MNC-spacing for enhancement of retention ability in MNC embedded gate stacks. It implies the possibility of reducing MNC spacing in DL structure of scaled memory devices by controlling the thickness of ILD.en
dc.language.isoenen
dc.relation.ispartofseriesApplied physics lettersen
dc.rights© 2012 American Institute of Physics. This paper was published in Applied Physics Letters and is made available as an electronic reprint (preprint) with permission of American Institute of Physics. The paper can be found at the following official DOI: [http://dx.doi.org/10.1063/1.4712565]. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper is prohibited and is subject to penalties under law.en
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuitsen
dc.titleStudy of charge distribution and charge loss in dual-layer metal-nanocrystal-embedded high-κ/SiO2 gate stacken
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.identifier.doi10.1063/1.4712565en
dc.description.versionPublished versionen
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