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Title: Circuit-simulated obstacle-aware Steiner routing
Authors: Shi, Yiyu
Mesa, Paul
Yu, Hao
He, Lei
Issue Date: 2007
Source: Shi, Y., Mesa, P., Yu, H., & He, L. (2007). Circuit-simulated obstacle-aware Steiner routing. ACM Transactions on Design Automation of Electronic Systems, 12(3).
Series/Report no.: ACM transactions on design automation of electronic systems
Abstract: This article develops circuit-simulated routing algorithms. We model the routing graph by an RC network with terminals as inputs, and show that the faster an output reaches its peak, the higher the possibility for the corresponding Hanan or escape node to become a Steiner point. This enables us to select Steiner points and then apply any minimum spanning tree algorithm to obtain obstaclefree or obstacle-aware Steiner routing. Compared with existing algorithms, our algorithms have significant gain on either wirelength or runtime for obstacle-free routing, and on both wirelength and runtime for obstacle-aware routing.
ISSN: 1084-4309
DOI: 10.1145/1255456.1255465
Rights: © 2007 ACM. This is the author created version of a work that has been peer reviewed and accepted for publication by ACMTransactions onDesign Automation of Electronic Systems, ACM. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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