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Title: Concurrent error detection in bit-serial normal basis multiplication over GF(2^m) using multiple parity prediction schemes
Authors: Lee, Chiou Yng
Meher, Pramod Kumar
Patra, Jagdish Chandra
Keywords: DRNTU::Engineering::Computer science and engineering::Computer systems organization::Computer-communication networks
Issue Date: 2010
Source: Lee, C. Y., Meher, P. K., & Patra, J. C. (2010). Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF (2^m) Using Multiple Parity Prediction Schemes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(8), 1234-1238.
Series/Report no.: IEEE transactions on very large scale integration (VLSI) systems
Abstract: New bit-serial architectures with concurrent error detection capability are presented to detect erroneous outputs in bit-serial normal basis multipliers over GF(2^m) using single and multiple-parity prediction schemes. It is shown that different types of normal basis multipliers could be realized by similar architectures. The proposed architectures can detect errors with nearly 100% probability.
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2009.2020593
Rights: © 2009 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [DOI:].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SCSE Journal Articles

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