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https://hdl.handle.net/10356/94362
Title: | Efficient systolic designs for 1- and 2-dimensional DFT of general transform-lengths for high-speed wireless communication applications | Authors: | Meher, Pramod Kumar Patra, Jagdish Chandra Vinod, Achutavarrier Prasad |
Keywords: | DRNTU::Engineering::Electrical and electronic engineering::Wireless communication systems | Issue Date: | 2010 | Source: | Meher, P. K., Patra, J. C., & Vinod, A. P. (2010). Efficient Systolic Designs for 1- and 2-Dimensional DFT of General Transform-Lengths for High-Speed Wireless Communication Applications. Journal of Signal Processing Systems, 60(1), 1-14. | Series/Report no.: | Journal of signal processing systems | Abstract: | In wireless communication, multiple receive-antennas are used with orthogonal frequency division multiplexing (OFDM) to improve the system capacity and performance. The discrete Fourier transform (DFT) plays an important part in such a system since the DFTs are required to be performed for the output of all those antennas separately. This paper presents area-time efficient systolic structures for one-dimensional (1-D) and two-dimensional (2-D) DFTs of general lengths. A low-complexity recursive algorithm based on Clenshaw’s recurrence relation is formulated for the computation of 1-D DFT. The proposed algorithm is used further to derive a linear systolic array for the DFT. The concurrency of computation has been enhanced and complexity is minimized by the proposed algorithm where an N −point DFT is computed via four inner-products of real-valued data of length ≈ (N/2). The proposed 1-D structure offers significantly lower latency, twice the throughput, and involves nearly the same area-time complexity of the corresponding existing structures. The proposed algorithm for 1-D DFT is extended further to obtain a 2-D systolic structure for the 2-D DFT without involving any transposition operation. | URI: | https://hdl.handle.net/10356/94362 http://hdl.handle.net/10220/7086 |
ISSN: | 1939-8018 | DOI: | 10.1007/s11265-008-0328-x | Rights: | © 2010 Springer. This is the author created version of a work that has been peer reviewed and accepted for publication by Journal of Signal Processing Systems, Springer. It incorporates referee's comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [DOI: http://dx.doi.org/10.1007/s11265-008-0328-x]. | Fulltext Permission: | open | Fulltext Availability: | With Fulltext |
Appears in Collections: | SCSE Journal Articles |
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70.Efficient Systolic Designs for 1.pdf | 1.75 MB | Adobe PDF | ![]() View/Open |
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