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|Title:||Exploiting parallelism by data dependency elimination : a case study of circuit simulation algorithms||Authors:||Wu, Wei
|Keywords:||DRNTU::Engineering::Mathematics and analysis::Simulations||Issue Date:||2012||Source:||Wu, W., Gong, F., Krishnan, R., Yu, H., & He, L. (2012). Exploiting Parallelism by Data Dependency Elimination: A Case Study of Circuit Simulation Algorithms. IEEE Design & Test of Computers, 1-1.||Series/Report no.:||IEEE design & test of computers||Abstract:||Considering the increasing complexity of integrated circuit (IC) designs at Nano-Tera scale, multi-core CPUs and many-core GPUs have provided ideal hardware platforms for emerging parallel algorithm developments in electronic design automation (EDA). However, it has become extremely challenging to leverage parallel hardware platforms at extreme scale beyond 22nm and 60GHz where the EDA algorithms, such as circuit simulation, show strong data dependencies. This paper presents data dependency elimination in circuit simulation algorithms such as parasitic extraction, transient simulation and periodic-steady-state (PSS) simulation, which paves the way towards unleashing the underlying power of parallel hardware platforms.||URI:||https://hdl.handle.net/10356/95237
|ISSN:||2168-2356||DOI:||10.1109/MDT.2012.2226201||Rights:||© 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/MDT.2012.2226201].||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Journal Articles|
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