Sensing margin enhancement techniques for ultra-low-voltage SRAMs utilizing a bitline-boosting current and equalized bitline leakage

Abstract

A small bitline sensing margin is one of the most challenging design obstacles for reliable ultra-low-voltage static random access memory (SRAM) implementation. This paper presents design techniques for bitline sensing margin enhancement using decoupled SRAMs. The proposed bitline-boosting current scheme improves the bitline sensing margin at a given bitline configuration. The bitline sensing margin can be further augmented by equalizing bitline leakage. Simulation using a 40-nm CMOS process shows that the proposed techniques achieve larger bitline sensing margin, wider operating temperature and supply range, and a larger number of cells per bitline.