Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/96165
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dc.contributor.authorYu, Hongyuen
dc.contributor.authorSun, Yuanen
dc.contributor.authorSingh, Navaben
dc.contributor.authorLo, Guo-Qingen
dc.contributor.authorKwong, Dim Leeen
dc.date.accessioned2013-07-10T07:22:21Zen
dc.date.accessioned2019-12-06T19:26:30Z-
dc.date.available2013-07-10T07:22:21Zen
dc.date.available2019-12-06T19:26:30Z-
dc.date.copyright2011en
dc.date.issued2011en
dc.identifier.urihttps://hdl.handle.net/10356/96165-
dc.description.abstractIn this review article, the scaling challenges of planar non-volatile memory, especially the flash-types including both floating gate-based and charge-trap-based devices are firstly discussed. The promising prospects brought by 3-Dimensional (3-D) nano-wire-based cells have been presented along with various device demonstrations and discussions on vertical nano-wire platform. The memory devices with highly scaled single-crystal Si nanowire (SiNW) channel and a gate-all-around (GAA) structure achieve superior program/erase (P/E) speed, cycling and high-temperature retention characteristics as compared to the planar one and are considered as promising candidate for future ultra-high non-volatile flash memory application.en
dc.language.isoenen
dc.relation.ispartofseriesMicroelectronics reliabilityen
dc.rights© 2011 Elsevier Ltd.en
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen
dc.titlePerspective of flash memory realized on vertical Si nanowiresen
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.identifier.doi10.1016/j.microrel.2011.10.025en
item.grantfulltextnone-
item.fulltextNo Fulltext-
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