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Title: Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model
Authors: Shang, Yang
Zhang, Chun
Yu, Hao
Tan, Chuan Seng
Zhao, Xin
Lim, Sung Kyu
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2013
Source: Shang, Y., Zhang, C., Yu, H., Tan, C. S., Zhao, X., & Lim, S. K. (2013). Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model. 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 693-698.
Abstract: 3D physical design needs accurate device model of through-silicon vias (TSVs). In this paper, physics-based electrical-thermal model is introduced for both signal and dummy thermal TSVs with the consideration of nonlinear electrical-thermal dependence. Taking thermal-reliable 3D clock-tree synthesis as a case-study to verify the effectiveness of the proposed TSV model, one nonlinear programming-based clock-skew reduction problem is formulated to allocate thermal TSVs for clock-skew reduction under non-uniform temperature distribution. With a number of 3D clock-tree benchmarks, experiments show that under the nonlinear electrical-thermal TSV model, insertion of thermal TSVs can effectively reduce temperature-gradient introduced clock-skew by 58.4% on average, and has 11.6% higher clock-skew reduction than the result under linear electrical-thermal model.
DOI: 10.1109/ASPDAC.2013.6509681
Rights: © 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Conference Papers

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