Please use this identifier to cite or link to this item:
Title: Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration
Authors: Lam, Siew-Kei
Srikanthan, Thambipillai
Clarke, Christopher T.
Keywords: DRNTU::Engineering::Computer science and engineering
Issue Date: 2012
Source: Lam, S.-K., Srikanthan, T., & Clarke, C. T. (2012). Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration. 2012 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC).
Abstract: Runtime reconfiguration is a promising solution for reducing hardware cost in embedded systems, without compromising on performance. We present a framework that aims to increase the advantages of runtime reconfiguration on reconfigurable processors that support full or partial runtime reconfiguration. The proposed framework incorporates a hierarchical loop partitioning strategy that leverages FPGA-aware merging of custom instructions to: 1) maximize the reconfigurable logic block utilization in each configuration, and 2) reduce the runtime reconfiguration overhead. Experimental results show that the proposed strategy leads to over 39% average reduction in runtime reconfiguration overhead for partial runtime reconfiguration. In addition, the proposed strategy leads to an average performance gain of over 32% and 34% for full and partial runtime reconfiguration respectively.
DOI: 10.1109/ReCoSoC.2012.6322889
Rights: © 2012 IEEE.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:SCSE Conference Papers

Citations 50

Updated on Feb 3, 2023

Page view(s) 20

Updated on Feb 3, 2023

Google ScholarTM




Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.