Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/97975
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dc.contributor.authorFahmy, Suhaib A.en
dc.contributor.authorMaskell, Douglas L.en
dc.contributor.authorCheah, Hui Yanen
dc.contributor.authorKulkarni, Chidamberen
dc.date.accessioned2013-07-25T06:15:55Zen
dc.date.accessioned2019-12-06T19:48:57Z-
dc.date.available2013-07-25T06:15:55Zen
dc.date.available2019-12-06T19:48:57Z-
dc.date.copyright2012en
dc.date.issued2012en
dc.identifier.citationCheah, H. Y., Fahmy, S. A., Maskell, D. L., & Kulkarni, C. (2012). A lean FPGA soft processor built using a DSP block. Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays.en
dc.identifier.urihttps://hdl.handle.net/10356/97975-
dc.identifier.urihttp://hdl.handle.net/10220/12233en
dc.description.abstractAs Field Programmable Gate Arrays (FPGAs) have advanced, the capabilities and variety of embedded resources have increased. In the last decade, signal processing has become one of the main driving applications for FPGA adoption, so FPGA vendors tailored their architectures to such applications. The resulting embedded digital signal processing (DSP) blocks have now advanced to the point of supporting a wide range of operations. In this paper, we explore how these DSP blocks can be applied to general computation. We show that the DSP48E1 blocks in Xilinx Virtex-6 devices support a wide range of standard processor instructions which can be designed into the core of a basic processor with minimal additional logic usage.en
dc.language.isoenen
dc.rights© 2012 ACM.en
dc.subjectDRNTU::Engineering::Computer science and engineeringen
dc.titleA lean FPGA soft processor built using a DSP blocken
dc.typeConference Paperen
dc.contributor.schoolSchool of Computer Engineeringen
dc.contributor.conferenceInternational symposium on Field Programmable Gate Arrays (2012)en
dc.identifier.doi10.1145/2145694.2145734en
item.fulltextNo Fulltext-
item.grantfulltextnone-
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